5-Level Paging and 5-Level EPT White Paper
https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf [software.intel.com]
2016-12-06 21:31
Existing processors limit linear addresses to 48 bits. Chapter 2 describes paging extensions that would relax that limit to 57 linear-address bits.